Part Number Hot Search : 
FR204 AN727 KTX301U 100BG D4001 X262AMR 100MR PEF20470
Product Description
Full Text Search

M38230G4-XXXFP - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V

M38230G4-XXXFP_1975342.PDF Datasheet
 
Part No. M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M38232G4-XXXFP M38232G4-XXXHP M38233G4-XXXFP M38233G4-XXXHP M38234G4-XXXFP M38234G4-XXXHP M38235G4-XXXFP M38230G6-XXXFP M38230G6-XXXHP M38231G6-XXXFP M38231G6-XXXHP M38232G6-XXXFP M38232G6-XXXHP M38233G6-XXXFP M38233G6-XXXHP M38234G6-XXXFP M38234G6-XXXHP M38235G6-XXXFP M38235G6-XXXHP M38236G6-XXXHP M38237G6-XXXFP M38237G6-XXXHP M38238G6-XXXFP M38230G7-XXXFP M38230G7-XXXHP M38231G7-XXXFP M38231G7-XXXHP M38232G7-XXXFP
Description 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
File Size 901.80K  /  76 Page  

Maker
Renesas Electronics Corporation.
Renesas Electronics, Corp.

Homepage
Download [ ]
[ M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M38232G4-XXXFP M38232G4-XXXHP M38233G4-XXXFP M38233G4-X Datasheet PDF Downlaod from Datasheet.HK ]
[M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M38232G4-XXXFP M38232G4-XXXHP M38233G4-XXXFP M38233G4-X Datasheet PDF Downlaod from Maxim4U.com ] :-)

[ View it Online ]   [ Search more for M38230G4-XXXFP ]

[ Price & Availability of M38230G4-XXXFP by FindChips.com ]
 Full text search : 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V

 Related Part Number
PART Description Maker
CY7C1371D-100AXI CY7C1371D-100BGI CY7C1373D-100BZI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 18兆位（为512k × 36/1M × 18）流体系结构，通过与NoBLTM的SRAM
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA119
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA119
 Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
CY62157DV3006 CY62157DV30L-55BVXE CY62157DV30L-55B 8-Mbit (512K x 16) MoBL㈢ Static RAM
8-Mbit (512K x 16) MoBL? Static RAM
8-Mbit (512K x 16) MoBL垄莽 Static RAM
8-Mbit (512K x 16) MoBL Static RAM
 Cypress Semiconductor
CY14B104L-BA15XCT CY14B104L-BA15XI 4 Mbit (512K x 8/256K x 16) nvSRAM 512K X 8 NON-VOLATILE SRAM, 15 ns, PBGA48
 Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
CY14B104MA-ZSP25XI CY14B104KA-ZS25XCT CY14B104KA C 4 Mbit (512K x 8/256K x 16) nvSRAM with Real-Time-Clock
512K X 8 NON-VOLATILE SRAM, 20 ns, PDSO44
 CYPRESS SEMICONDUCTOR CORP
CY7C1387D-250AXC CY7C1386D-167BGC CY7C1386D-167BGX 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM 1M X 18 CACHE SRAM, 3 ns, PBGA119
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA119
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA165
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM 512K X 36 CACHE SRAM, 3 ns, PQFP100
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM 1M X 18 CACHE SRAM, 3 ns, PQFP100
 Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
CY7C1460AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(带NoBL结构6-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
 Cypress Semiconductor Corp.
SST29VF010-70-4C-NH SST29SF010-70-4C-NH SST29SF040 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 256K X 8 FLASH 5V PROM, 55 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 512K X 8 FLASH 2.7V PROM, 55 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 128K X 8 FLASH 2.7V PROM, 55 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 512K X 8 FLASH 5V PROM, 55 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 128K X 8 FLASH 5V PROM, 55 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 128K X 8 FLASH 5V PROM, 55 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 512K X 8 FLASH 2.7V PROM, 55 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 256K X 8 FLASH 2.7V PROM, 55 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 64K X 8 FLASH 5V PROM, 55 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 512K X 8 FLASH 5V PROM, 55 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 256K X 8 FLASH 5V PROM, 55 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 128K X 8 FLASH 2.7V PROM, 70 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 128K X 8 FLASH 2.7V PROM, 70 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 256K X 8 FLASH 2.7V PROM, 70 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 128K X 8 FLASH 5V PROM, 70 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 64K X 8 FLASH 5V PROM, 70 ns, PDIP32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 512K X 8 FLASH 5V PROM, 70 ns, PDIP32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 256K X 8 FLASH 5V PROM, 70 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 64K X 8 FLASH 5V PROM, 70 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 256K X 8 FLASH 5V PROM, 70 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 256K X 8 FLASH 5V PROM, 70 ns, PDIP32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 512K X 8 FLASH 5V PROM, 70 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 512K X 8 FLASH 5V PROM, 70 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 64K X 8 FLASH 2.7V PROM, 70 ns, PQCC32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 64K X 8 FLASH 2.7V PROM, 70 ns, PDSO32
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash 512千位/ 1兆位/ 2 4兆位（8）小部门闪光
 Silicon Storage Technol...
SILICON STORAGE TECHNOLOGY INC
Elektron Technology PLC
Silicon Storage Technology, Inc.
CY62148DV30 CY62148DV30LL-55BVI CY62148DV30L-55ZSX 4-Mbit (512K x 8) MoBL垄莽 Static RAM
4-Mbit (512K x 8) MoBL? Static RAM
 Cypress Semiconductor
IS41C85120-60K IS41C85120-60KI IS41C85120-35K IS41 512K x 8 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE 512K X 8 EDO DRAM, 60 ns, PDSO28
 Integrated Silicon Solution, Inc.
ISSI[Integrated Silicon Solution, Inc]
CY62148EV30LL-45BVXI CY62148EV30LL-55SXI CY62148EV 4-Mbit (512K x 8) Static RAM 512K X 8 STANDARD SRAM, 55 ns, PDSO32
4-Mbit (512K x 8) Static RAM 512K X 8 STANDARD SRAM, 45 ns, PDSO32
 Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
CY7C1382DV25-250BZC CY7C1382DV25-200BZC CY7C1382DV 18-Mbit (512K x 36/1M x 18) Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Pipelined SRAM 1M X 18 CACHE SRAM, 3 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Pipelined SRAM 1M X 18 CACHE SRAM, 3.4 ns, PBGA119
18-Mbit (512K x 36/1M x 18) Pipelined SRAM 1M X 18 CACHE SRAM, 3 ns, PBGA119
 Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
 
 Related keyword From Full Text Search System
M38230G4-XXXFP siliconix M38230G4-XXXFP Datasheet M38230G4-XXXFP quad op amp M38230G4-XXXFP max M38230G4-XXXFP 器件参数
M38230G4-XXXFP toshiba M38230G4-XXXFP ic资料查询 M38230G4-XXXFP Bus M38230G4-XXXFP Serie M38230G4-XXXFP Signal
 

 

Price & Availability of M38230G4-XXXFP

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X
7.2118518352509